1. Field of the Invention
The present invention relates to an automatic equalizer that compensates a received signal that has been subject to distortion due to intersymbol interference, and in particular, relates to a technology for constraining the survivor paths based on the regularity of the code.
2. Description of the Related Art
Conventionally, a received signal has distortions due to the condition of its transmission channel. One method of compensating this distortion is using an automatic equalizer at the receiver. Here, a conventional automatic equalizer is explained referring to FIG. 8.
FIG. 8 is a structural drawing of a conventional automatic equalizer.
In FIG. 8, reference numeral 501 is an estimation receiving circuit that generates kM estimated received signals by convolutionally processing kM series of candidate signals Sscan that are a combination of transmitted code having an M chip length (where M is a natural number) and k levels (where k is a natural number) and the impulse response h of a transmission channel having length M, and outputs these generated kM estimated received signals Ser. These kM estimated received signals Ser are the signals that are estimated to be the received signals Sr.
Reference numeral 502 is a subtracter that generates kM estimated error signals Serr by subtracting the kM estimated received signals Ser, from the received signal Sr, and outputting these generated kM estimated error signals Serr.
Reference numeral 503 is a Viterbi logic circuit that is structured from the path metric calculating circuit 504 and the survivor path selection circuit 505, described below.
Reference numeral 504 is a path metric calculating circuit that inputs the kM estimated error signals Serr and the kMxe2x88x921 survivor path metric signals Spmsv corresponding to each state of a trellis diagram, squares the absolute value of the kM estimated error signals Serr corresponding respectively to the kMxe2x88x921 survivor path metric signals Spmsv to generate kM path metric signals Spm, and outputs these generated kM path metric signals Spm.
Reference numeral 505 is a survivor path selection circuit that inputs the kM path metric signals Spm, determines the smallest among the kM path metric signals Spm for each kMxe2x88x921 states, outputs these as kMxe2x88x921 survivor path metric signals Spmsv, and at the same time, among the kM series of candidate signals Sscan, outputs as the decision output signals Sd a portion of the series of candidate signals Sscan corresponding to the smallest among the kMxe2x88x921 survivor path metric signals Spmsv. That is, the survivor path selection circuit 505 carries out the code decision of the received signals.
Reference numeral 506 is an error correction circuit that generates an error correction decision output signal Sed by correcting the decision output signal Sd by the regularity of the code, and outputs this generated error correction decision output signal Sed.
However, the conventional automatic equalizer as described above carries out error correction using the error correction circuit 502 after code the decision, and thus in the case that an error in the code decision is propagated, the error correction effect by the error correction circuit 502 is diminished.
Therefore, in consideration of this problem, it is an object of the present invention to provide a technology that can resolve the above-described problem, and improve the error correction effect even in the case that an error in the code decision in the automatic equalizer is propagated.
The above described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a kM series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the kM series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting the generated kM estimated error signals; a constraint condition selection circuit that inputs the received signal, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs this generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the kM series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates decision output signals based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a kM series of candidate signals that are combinations of a transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the kM series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting the generated kM estimated error signals; a constraint condition selection circuit that inputs decision output signals, generates constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the kM series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates decision output signals based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a kM series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), kMxe2x88x921 hypothetical output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out convolutional processing of the combination of the kM series of candidate signals and the kMxe2x88x921 hypothetical output signals respectively corresponding to the kM series of candidate signals and the transmission impulse response having a length (M+N); a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting the generated kM estimated error signals; a constraint condition selection circuit that inputs the received signal, generates constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals, the kMxe2x88x921 hypothetical output signals, and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the kM series of candidate signals, and the kMxe2x88x921 hypothetical output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates the decision output signals and kMxe2x88x921 hypothetical output signals for each state of a trellis diagram by carrying out code decisions based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals and the kMxe2x88x921 hypothetical output signals for each state of the trellis diagram.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a kM series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), kMxe2x88x921 hypothetical output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out convolutional processing on the combination of the kM series of candidate signals and the kMxe2x88x921 hypothetical output signals respectively corresponding to the kM series of candidate signals, and the transmission impulse response having a length (M+N); a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting these generated kM estimated error signals; a constraint condition selection circuit that inputs the decision output signals, generates a constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals, the kMxe2x88x921 hypothetical output signals, and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the kM series of candidate signals, and the kMxe2x88x921 hypothetical output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates the decision output signals and kMxe2x88x921 hypothetical output signals for each state of a trellis diagram by carrying out code decisions based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals and the kMxe2x88x921 hypothetical output signals for each state of the trellis diagram.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a kM series of candidate signals that are combinations of transmitted code having M chip length (where M is a natural number) and k levels (where K is a natural number), a decision output signal having an N chip length (where N is a natural number), and a transmission channel impulse response-having a length (M+N), and estimates a received signal by carrying out convolutional processing on the combination of the kM series of candidate signals and the kMxe2x88x921 hypothetical-output signals respectively corresponding to the kM series of candidate signals with the transmission impulse response having a length (M+N) and outputs the estimated kM estimated received signals; a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting these generated kM estimated error signals; a constraint condition selection circuit that inputs the received signal, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals, the decision output signal, and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the kM series of candidate signals, and the decision output signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates decision output signals based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a kM series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), decision output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out combinational processing of the combination of the kM series of candidate signals and the kMxe2x88x921 hypothetical output signals respectively corresponding to the kM series of candidate signals with the transmission impulse response having a length (M+N) and outputting the estimated kM estimated received signals; a subtracter that inputs the received signal and the kM estimated received signals, generates kM estimated error signals by subtracting each of the kM estimated received signals from the received signal, and outputting these generated kM estimated error signals; a constraint condition selection circuit that inputs the decision output signals, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs these generated constraint condition selection signal; a constraint condition generation circuit that inputs the kM series of candidate signals, the decision output signals, and the constraint condition selection signal, determines the constraint condition for each of kMxe2x88x921 states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents, the kM series of candidate signals, and the decision output signals, and outputs the constraining condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the kM estimated error signals and the constraint condition signal, generates the decision output signals based on the kM estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the kM estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each state of the trellis diagram, calculates the absolute value of the KM estimated error signals respectively corresponding to the kMxe2x88x921 survivor path metric signals, and outputs the generated kM path metric signals, and a survivor path selection circuit that inputs the kM path metric signals and the constraint condition signal, determines among the kM path metric signals the one for which the state transition in the trellis diagram satisfy and minimize the constraint condition represented by the constraint condition signal for each of kM conditions, and outputs the result as the kMxe2x88x921 survivor path metric signals, and at the same time outputs as decision output signals a specified portion of the kM series of candidate signals corresponding to those for which the kMxe2x88x921 series of candidate signals are minimal.
In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the kM estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each state of the trellis diagram, calculates the absolute value of the KM estimated error signals respectively corresponding to the kMxe2x88x921 survivor path metric signals, and outputs the generated kM path metric signals, and a survivor path selection circuit that inputs the kM path metric signals and the constraint condition signal, determines among the kM path metric signals those for which the state transition in the trellis diagram satisfy and minimize the constraint condition represented by the constraint condition signal for each of kM conditions, and outputs the result as the kMxe2x88x921 survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the kM series of candidate signals respectively corresponding to the kMxe2x88x921 survivor path metric signals, and outputs as decision output signals a specified portion of the kM series of candidate signals corresponding to those among the kMxe2x88x921 survivor path metric signals that are minimal.
In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the kM estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each state of the trellis diagram, squares the absolute value of the kM estimated error signals corresponding respectively to the kMxe2x88x921 survivor path metric signals, and outputs the results as kM path metric signals, a path metric offset circuit that inputs the kM path metric signals and the constraint condition signal, and outputs kM offset path metric signals having added a specified offset value only to those among the kM path metric signals for which the state transitions of the trellis diagram do not fulfill the constraint conditions represented by the constraint condition signal, and a survivor path selection circuit that inputs the kM offset path metric signals, determines for each of the kMxe2x88x921 state those among the kM offset path metric signals that are minimal, and outputs the result as the kMxe2x88x921 survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals among the kM series of candidate signals for which the corresponding kMxe2x88x921 survivor path metric signals are minimal.
In addition, the Viterbi calculation circuit is characterized in comprising a path metric calculation circuit that inputs the kM estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each state of the trellis diagram, and outputs the kM path metric signals having added the square of the absolute value of the kM estimated error signals corresponding respectively to the kMxe2x88x921 survivor path metric signals, a path metric offset circuit that inputs the kM path metric signals and the constraint condition signal, adds a specified offset value only to those among the kM path metric signals for which the state transition in the trellis diagram does not satisfy the constraint condition represented by the constraint condition signal, and outputs the result as kM offset path metric signals, and a survivor path selection circuit that inputs the kM offset path metric signals, determines among the kM offset path metric signals those that are minimal for each of kMxe2x88x921 conditions, and outputs the result as the kMxe2x88x921 survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals among the kM series of candidate signals that correspond respectively to the kMxe2x88x921 survivor path metric signals, and in addition, outputs as the decision output signals a specified portion of the series of candidate signals among the kM series of candidate signals those for which the corresponding kMxe2x88x921 survivor path metric signals are minimal.
In addition, the Viterbi calculation circuit is characterized in comprising an estimated error offset circuit that inputs the kM estimated error signals and the constraint condition signal, and among the kM estimated error signals, outputs the kM offset estimated error signals having added a specified offset value only to those for which the state transitions in the trellis diagram do not satisfy the constraint condition represented by the constraint condition signal, a path metric calculation circuit that inputs the kM offset estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each condition of the trellis diagram, and outputs kM path metric signals to which square of the absolute value of the kM offset estimated error signals corresponding respectively to the kMxe2x88x921 survivor path metric signals has been added, and a survivor path selection circuit that inputs the kM path metric signals, determines for each of kMxe2x88x921 conditions those among the kM path metric signals that become minimum, and output the result as kMxe2x88x921 survivor path metric signals, and at the same time outputs as decision output signals a specified portion of the series of candidate signals corresponding to those among the kM series of candidate signals for which kMxe2x88x921 survivor path metric signals are minimal.
In addition, the Viterbi calculation circuit is characterized in comprising an estimated error offset circuit that inputs the kM estimated error signals and the constraint condition signal, and outputs the kM offset estimated error signals having added a specified offset value only to those among the kM estimated error signals for which the state transitions in the trellis diagram do not satisfy the constraint condition represented by the constraint condition signal, a path metric calculation circuit that inputs the kM offset estimated error signals and the kMxe2x88x921 survivor path metric signals corresponding to each state of the trellis diagram, and outputs kM path metric signals to which square of the absolute value of the kM offset estimated error signals corresponding respectively to the kMxe2x88x921 survivor path metric signals has been added, and a survivor path selection circuit that inputs the kM path metric signals, determines for each of kMxe2x88x921 conditions those among the kM path metric signals that become minimum, and output the result as kMxe2x88x921 of survivor path metric signals, and at the same time outputs as hypothetical output signals a specified portion of the series of candidate signals respectively corresponding to the kMxe2x88x921 survivor path metric signals, and in addition, outputs as decision output signals a specified portion of the series of candidate signals corresponding to those among the kM series of candidate signals for which kMxe2x88x921 survivor path metric signals that become minimum.
In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference provides a means for detecting regularity in the code of the received signals, a means for calculating and outputting the path metric signals for each condition of the received signal, and a means that determines as the most likely states those states of the received signals that satisfy the detected regularity of the code of the received signal and have minimal path metric signals.
In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference provides a means for detecting regularity in the code of the received signals, a means for calculating and outputting the path metric singles for each condition of the received signal, a means for determining whether or not the received signal satisfies the detected regularity of the code of the received signals, and only in the case that as a result of the decision the received signal satisfies the regularity of the code, adds a specified offset value to the path metric signals, and a means that determines as the most likely states those states of the received signals that satisfy the detected regularity of the code of the received signal and have minimal path metric signals.
In addition, the above-described problems are resolved by an automatic equalizer that compensates a received signal that has been distorted by intersymbol interference, provides a means that generates a plurality of estimation received signals that estimate received signals by using convolutional processing, a means that generates a plurality of estimated error signals by subtracting each of the estimated received signals from the received signal, a means for detecting regularity in the code of the received signal, a means for determining whether or not the received signal satisfies the detected regularity of the code of the received signal, and only in the case that as a result of the decision the received signal satisfies the regularity of the code, adds a specified offset value to the path metric signals, a means that calculates and outputs path metric signals in each state of the received signal from the estimated error signals, and a means that determines as the most likely states those states of the received signal that have minimal path metric signals.
In particular, the means that detects the regularity of the code in the received signals is characterized in detecting the regularity of the code based on the received signals that have already been received. The means for detecting the regularity of the code in the received signals is characterized in detecting the regularity of the code based on the condition of the most likely received signals determined by the control means.
That is, in the present invention, errors in code determination are reduced by constraining the selection of survivor paths based on the regularity of the code.